1. Field of the Invention
The present invention relates to a semiconductor device and a method of producing the same. More particularly, the present invention relates to a semiconductor device of a type called a system-in-package (SiP), which is packaged at a wafer level, and a method of producing the same.
2. Description of the Related Art
Demands for more compact, thinner and lighter portable electronic devices, such as a digital video camera, a digital cellular phone and a notebook computer, continue to increase. To respond thereto, seven tenths of reduction has been realized in three years in recent VLSI and other semiconductor devices, while studies and developments have been made on a significant issue of how to improve packaging density of components on a board (printed wiring board) in an electronic circuit device wherein such a semiconductor device is mounted on a printed wiring board.
For example, a package type of a semiconductor device has shifted from the lead inserted type, such as a dual inline package (DIP), to the surface mounted type and, furthermore, a flip-chip mounting method for providing a bump (projecting electrode) made of solder or gold on a pad electrode of a semiconductor chip and connecting to the wiring board via the bump with the surface directing downward has been developed.
In the above semiconductor device, when forming multilayer wiring, also known as the re-wiring of layers on the semiconductor substrate (chip), for example, an insulating layer is formed to have a film thickness of 1 μm or less on a surface of a semiconductor wafer having formed therein a transistor and another semiconductor element by the chemical vapor deposition (CVD) method, the sputtering method, the thermal oxidization method or the spin coating, etc., and dicing processing is performed to obtain a small piece of the semiconductor device.
In the above production method, even when a step is generated on the insulating layer and a curvature arises on the wafer, it has been sufficient to watch out only for the blade and chipping during dicing, such that it has been unnecessary to give attention to the step disconnection of a resist and the curvature of the wafer.
Furthermore, the development of a complicated type of package called a system-in-package (SiP) has advanced, wherein a passive element, such as a coil, and another semiconductor chip are buried in an interlayer of an insulating layer for insulating re-wiring layers formed on a semiconductor substrate (chip) and packaged at a wafer level.
A method for producing the SiP includes, for example, stacking a plurality of insulation layers made by a polyimide resin, etc. on a surface of a semiconductor wafer having formed therein a transistor and another semiconductor element and forming wiring by burying between the respective insulation layers, resulting in a configuration wherein a re-wiring layer composed of a plurality of wiring layers is formed by burying in the insulation layers. The insulation layers and the semiconductor wafer are cut along a scribe line (dicing), so that a semiconductor made to be a SiP on the wafer level can be produced.
As to the above plurality of insulation layers, even when a film thickness per one layer is made to be at least 10 μm, it becomes 30 μm when three of these layers are stacked. When forming a coil and another passive element between the insulation layers and when burying a semiconductor chip, it becomes even thicker. Thus, for example, if the semiconductor wafer (substrate) is made to be as thin as 50 μm or so, relatively, the film thickness of insulation layers of the re-wiring layer cannot be ignored and a curvature arises on the semiconductor wafer due to, for example, a difference of thermal expansion coefficients between the semiconductor wafer and the insulation layer portion.
Therefore, in a SiP type semiconductor device configured by stacking a plurality of resin layers on a semiconductor chip and burying re-wiring layers in the resin layers, a semiconductor device formed to be a stepwise shape by sides and upper surfaces of respective resin layers and an upper surface of a semiconductor chip has been developed.
FIG. 1A is a sectional view around a scribe line of a semiconductor wafer on which a plurality of semiconductor chips are integrated to form the above semiconductor device.
In each semiconductor chip region of the semiconductor wafer 10 on which semiconductor chips having an electronic circuit formed therein including a transistor or other semiconductor element are integrated, an insulation layer configured by stacking a first resin layer 20, a second resin layer 21, a third resin layer 22 and a fourth resin layer 23, a wiring layer composed of a first wiring layer (30, 31), a second wiring layer (32, 33) and a third wiring layer (34 and 35) are formed by being buried in the insulation layer composed of these stacked resin layers, and a wiring layer (not shown) connected thereto is formed also on the fourth resin layer 23.
In the semiconductor wafer 10 on which the above semiconductor chips are integrated, side surfaces and upper surfaces of the respective resin layers and an upper surface of the semiconductor wafer are formed as a stepwise shape, and a scribe line L is exposed, so that stress in not imposed upon the semiconductor wafer and curvature does not arise.
On the other hand, in the above SiP type semiconductor device, there is known the configuration of providing a buffer layer having a stress buffering function to improve secondary connection reliability with a board, and connecting to a bump, such as solder, via a post made of copper through the buffer layer.
Steps below are performed to form a buffer layer, a post and a bump on the semiconductor wafer having the configuration shown in FIG. 1A.
First, as shown in FIG. 1B, the post 36 made of copper is formed by connecting to a wiring layer (not shown) formed on the fourth resin layer 23 on the semiconductor wafer 10 on which semiconductor chips are integrated to be the configuration as shown in FIG. 1A.
Next, as shown in FIG. 2A, a resin having a stress buffering function, such as a polyamideimide resin, is supplied all over the post 36, for example, by a screen printing method, etc. to form the buffer layer 24. The buffer layer 24 is formed by burying the scribe line.
Next, as shown in FIG. 2B, the top of the post 36 is exposed on the upper surface of the buffer layer 24 by polishing, furthermore, a bump 37, such as a solder ball, is formed to be connected to the post 36.
Next, as shown in FIG. 3, by cutting (dicing) the semiconductor wafer 10 along scribe lines SL using a dicing blade B, a semiconductor device made to form a SiP on the wafer level of a bump connection type via the buffer layer can be produced.
However, as shown in FIG. 2A, when the buffer layer is formed all over by burying the scribe lines, curvature arises on the semiconductor wafer due to the same reasons curvature arises when an insulation layer of a resin is formed all over.
Curvature arising on the semiconductor wafer may cause any number of problems, including a mounting defect of a solder ball to be mounted as the above bump 37, unevenness of height when forming bumps by printing, adsorption error of a handling apparatus in a wiring step of the upper layer and in a plating step, and unevenness of height when the wafer is finally cut into pieces.
Also, the scribe lines are hidden by the buffer layer, and alignment marks and a name of a type of the production to be produced normally formed on the scribe lines cannot be seen.
Therefore, in the cutting (dicing) step shown in FIG. 3, positions of the bumps have to be alignment targets of scribe, which causes a mistake in the dicing operation such that workability declines.
Furthermore, there is no other way to confirm the name of the type of the semiconductor wafer other than by confirming the positions of the bumps, resulting in further decreases in workability.
Furthermore, in the cutting (dicing) step shown in FIG. 3, since the buffer layer and the semiconductor substrate are cut together, the cutting speed of the dicing can be raised only as high as 10 mm/s or so, and throughput of the production steps is hard to improve.